Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
نویسندگان
چکیده
منابع مشابه
Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-lm gates patterned by nanostencil lithography
0167-9317/$ see front matter 2012 Elsevier B.V. A http://dx.doi.org/10.1016/j.mee.2012.07.048 ⇑ Corresponding author. E-mail address: [email protected] (D. Sacch We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nan...
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Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction cha...
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ژورنال
عنوان ژورنال: IEEE Journal of the Electron Devices Society
سال: 2015
ISSN: 2168-6734
DOI: 10.1109/jeds.2015.2441736